Hi everyone. today I'm going to discuss about how the back cell power delivery is helping in the chip design, to reduce the IR drop. That means power ation in the chip and improve the performance and even improve the signal integrity, between the. Signals in the design or in the chip, like how it is helping, through the chip. I'm going to discuss on this more in my coming slides. So coming to that backside power delivery network. Now, we'll call it as A-B-S-P-D-N. It's a technology currently, or opting, like in the. Two m below that, two nanometer below that technologies. So it's a revolutionary because earlier visit to have that, whole, the power delivery on the front side of the design. Along with the signals. So suppose like if you have the metal layers of 15, then the top metal layers will go for power and the next metal layers will go for the clock, and the remaining metal layers is go for. Signal. So because of that, we can't use all the metal layers but signals and there is no availability of the, for the routing resources, for the signals. Because of that, we move that most of the backside, most of the power routes in the backside through nano silicone. Through Silicon vs. We are making like a reducing the stop state of the chip and we are putting like a sending the VS through that to connect that backside power. So it's a revolution in the chip design currently opting like, many of the lower level node like Intel, TSMC and Samsung. This actually earlier as I mentioned, the power and signal are in the, of the design, but here we are moving that entire power into the backside of the design. And, we are using like, continue this one to the. DS V. This is helping like a significant improvement in the performance, efficiency and power. So this incorporat like silicon. We, for that power delivery through Silicon Subrate, we are attending like a silicon subrate. substrates. SUBRATE means it's a CMOs device. There's a substrate in the CMOs device. So we are making like as much as, thinning because of, to connect that backside power with the front side of the design. Integrating that front side of the design with, through silicon V is routing congestion, air drop, improving that activity. In Intel's power via implementation and further developments are going in the other manufacturers like TSMC and Samsung. So I'm going to discuss more about on this in my coming slides. So if you're coming to that traditional power delivery limitations, these are routing congestion in advanced, the five nanometer and below there will be like, Most of that 40% of our routing resources is control by the power delivery. And, remaining goes to the clock and signal as, metal just carrying down in the lower technology to 24 nanometer higher drop increasing dramatically by 45% compared with the previously technology notes. So it's a severely constrained in the signal routing options because we don't have the, routing sources for the signals. So for this, we are moving to that, the backside power. And also there is a other disadvantage, water degradation. like the technologies are, going down, like we are going towards the two nanometer. So the what is operating, what is also will come down now, like 0.7 volts and, it drops. What? It drops also significantly 20 15% across the day during the high competition loads. Even like in the critical corners, it's increasing like 16.5%. So this is like another disadvantage, with the front side. So there is a power supply noise. Currently the dynamic Power Circuit operation generates a substantial power supply. Noise is reaching, 85 to 95 MTSS peak to peak, under typical workloads. This is a regular, normal, power turbine, supplies. And in place fluctuations, said 22% from nominal values, security and timing. Predictability. So this p report delivery, very hard feature, how it'll be the, as I mentioned earlier, they were processing, we reading that, this substrate as much as less possible to make it like, to get high yield. Along with that, With, battery yield and reducing that substrate sub subrate to 12 to 50 micron thickness with exceptional control maintained within 45 micron, across the 300 millimeter wave advanced TV fabrication use, remarkable s of, 10 to one in, backside Power delivery is a featuring like ultra fine via diameters under to 200 nanometer and beside depth exceeding to. 2.5 microns. So power level implementation, specialized backside. Metal stack utilizing advanced copper metalization techniques. Use low sheet resistance of, point knot one five, m for the engineered three layer power distribution network with optimized 4.2 micrometer thickness, delivers substantial, 58% reduction in the. PDN implements, compared to conventional approaches, the system benefits significant election in, required met layer from conventional, like conventional 10 to 12, like 10 to 15 even, met layers. Now it is, we are moving to 7, 2 8, for the same, frequency, so signal. Interconnect length decreases by 25% and that they contributing to the dynamic traumatic cause delay improvement of 35% while cement signal pro stock by 42% because of, more routing sources available for the signals. So it improves the performance and it's a state and weak power as, there are more vs for the, power. And the more routings is available for the signal, there will be less crosstalk. So if you're comparing the performance between the traditional, power delivery network and backside power delivery network, the sistance is, traditional. It is like one 50% and ambassador power, it is a hundred percent the poor concept. What for, If you're comparing with the WA four millimeters squared, then it is 2.5 in the conventional and 1.75, and a metal area says it is 35% and 15% in the backside power delivery. Pdn, it is a hundred percent, 155% I drop it is a hundred percent in the, if you're comparing with a hundred percent, then it'll be like 40% with the B-S-P-D-N. Metal layers will be calmed down. It is if you are getting with eight in the traditional, and it'll be like three. So while manufacturing, we have to capture these things. We tending, tending or to five to 10 microns, with exceptional surface integration below two nanometer or Ness TS integration. Hi Christian, 500 nanometer TSP featuring industrial leading tenish. One has aspect ratio with the near vertical, 89.8 plus or minus 0.2, decreased side wall profiles, and the thermal management TSV replacement architecture, the critical thermal grads by 40%, enhancing the device reliability. So these are like the helping the, we have to catch the, this while manufacturing for the back still power delivery. So design methodology, observation, so machine learning optimization, 68% action in design cycles with, 40% I improvement and power delivery network. Advanced simulation dose. If you, with the 3D Electromatic technology achieving like it's a 94% coalition with the whatever we get with the actual silicon. post silicon measurements, power ga certific like best, TSV placement algorithms. Will it reduce like the higher drop voltage drop by 48% across critical path? The most of the leading, companies that are opting this, backside power delivery currently. So this will reduce like the thermal disp and improve the current density across, different, multiple designs. The, even the run time. Also with that one, the run time will be increased by 70% improvement. The, it'll exit the time to market of the designs. So these are measure players currently opting the backside power delivery intel power via currently Intel is opted, the old means 7.8 er, the Intel, latest technology. It is the current, TSMs. Latest technology. TSMC, not at comeback, but Intel is working on this 1.8 nanometer. so faster. Updated in the intel, technologies. Intel latest technologies, it's actually like a 30%, power delivery, efficiency, and, the current, improvement. Also, it's a 2.8 amps for millimeter square. While maintain like a four plus or minus 4% voltage regulation across the day. TSMC has invested like the 2.8 billion on this backstory, power delivery. They're working on this, demonstr, exceptionally like 28% power efficiency with, their predicting and with the 15% performance improvement. In the two M process node, Samsung Hal up to this one, vertical power delivery with the TSVs. one 50 nanometer diameters with the same finished one as aspect of TSVs advanced Metalation Techniques Seal 2.2 x electronic. Aggression resistance, computation, power delivery architectures with this, Samsung technologies. So feature aspects 2025 and beyond. I said 25%. market adoption in the. 2025. predicting for the, high performance computing and, mobile applications, say 25% predicting will adopt this, backside power delivery with the latest advance nodes. And a market opportunity is like 85 5 billion. for the technology integration across semi sectors, 40%, efficiency improvement for efficiency gains in, next generation sites, rising advanced, the, BSPD and our teacher with, compared to that conventional, front cell power delivery, the current density entity, it's for four ramps for millimeter square peak current handling capacity while maintaining precise, plus minus 3.5%, across all regulations. Advanced research insureds now exit towards, breakthrough BSPD and implementations with the unprecedented specific teams are developing ultra mini TSP structures, with the diameters below hundred nanometer and, revolutionary one. currently like we are, How the 300 nanometer and a 200 nanometer TSPs, so the current, they're working on to reduce that, diameters to hundred nanometer and, expect of the list. One, it'll improve the width and the depth of that. we. And also the junction temperature, beyond and improving that current, density. So the work is still going on. This. so for metrics across manufacturers for change, implement inte leads with the 30% improvement followed by TS MC 28%, and Samsung at 25% with their backside power delivery implementations. TSV yield rates closely intellectual, high manufacturing patient with, 19.95 TSV rate while TSMC and, Samsung, follows by closely by 98, 99 0.8 and 99.7. Current density city, power via technology enabled intel to reach 2.8 times for millimeters square. and the Samsung and TSM just, logging on this, Just below, temperature reduction. All manufacture choose, significant cooling benefits with, inate using temperature by eight degrees ingrade while t Samsung seven degrees. The temperature is, performs metrics for the back power delivery, feature. Implications, density improvement implement is not just transfer density improvement. Also, along with the performance improvement, competition powerment, it is like 25% improvement. with the traditional delivery network, the power is reduced by 35, 2 40% with the different metal layers, performance enhancements. Overall performance efficiency improved by 2020 5% with the dynamic power, reduction. 30% in, high performance competing measurement, and 35% who design flexibility separation of power and signal. do domains enable 30 reduction in routing complexity. It'll reduce the routing resources with the average violent, also will come down to 2020 5% required, metal air reduction from, it'll also come down to. Metal layers right into instructed while we are going with the less metal layers. 78, for the same functional 8%, 18% delay reduction. Economic impact and co conclusions. ancient cost of this, will increase 18 to 22%. return of vestment timelines will be like, 15, 12, 20 months For data center implementations, yield, implement 80%, higher than conventional process, then cycle at 25% reduction design cycle enrollment, cycle time. this is, as a advanced technology. Currently most of the lower technology nodes, we are, adopting in the lower technology nodes. in the cheap design. So for the, to reduce the power and improve the performance and, reduce the ity issues. So thank you. Thank you for listening. Thank you very much.